Tech

The FPGA Chip Is an IEEE Milestone

Published

4 months ago

April 28, 2026

Many of the world’s most advanced electronic systems—including Internet routers, wireless base stations, medical imaging scanners, and some artificial intelligence tools—depend on field-programmable gate arrays. Computer chips with internal hardware circuits, the FPGAs can be reconfigured after manufacturing.

On 12 March, an IEEE Milestone plaque recognizing the first FPGA was dedicated at the Advanced Micro Devices campus in San Jose, Calif., the former Xilinx headquarters and the birthplace of the technology.

The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly.

The ceremony, which was organized by the IEEE Santa Clara Valley Section, brought together professionals from across the semiconductor industry and IEEE leadership. Speakers at the event included Stephen Trimberger, an IEEE and ACM Fellowwhose technical contributions helped shape modern FPGA architecture. Trimberger reflected on how the invention enabled software-programmable hardware.

Solving computing’s flexibility-performance tradeoff

FPGAs emerged in the 1980s to address a core limitation in computing. A microprocessor executes software instructions sequentially, making it flexible but sometimes too slow for workloads requiring many operations at once.

At the other extreme, application-specific integrated circuits are chips designed to do only one task. ASICs achieve high efficiency but require lengthy development cycles and nonrecurring engineering costs, which are large, upfront investments. Expenses include designing the chip and preparing it for manufacturing—a process that involves creating detailed layouts, building masks for the fabrication machines, and setting up production lines to handle the tiny circuits.

“ASICs can deliver the best performance, but the development cycle is long and the nonrecurring engineering cost can be very high,” says Jason Cong, an IEEE Fellow and professor of computer science at the University of California, Los Angeles. “FPGAs provide a sweet spot between processors and custom silicon.”

Cong’s foundational work in FPGA design automation and high-level synthesis transformed how reconfigurable systems are programmed. He developed synthesis tools that translate C/C++ into hardware designs, for example.

At the heart of his work is an underlying principle first espoused by electrical engineer Ross Freeman: By configuring hardware using programmable memory embedded inside the chip, FPGAs combine hardware-level speed with the adaptability traditionally associated with software.

The FPGA architecture originated in the mid-1980s at Xilinx, a Silicon Valley company founded in 1984. The invention is widely credited to Freeman, a Xilinx cofounder and the startup’s CTO. He envisioned a chip with circuitry that could be configured after fabrication rather than fixed permanently during creation.

Articles about the history of the FPGA emphasize that he saw it as a deliberate break from conventional chip design.

At the time, semiconductor engineers treated transistors as scarce resources. Custom chips were carefully optimized so that nearly every transistor served a specific purpose.

Freeman proposed a different approach. He figured Moore’s Law would soon change chip economics. The principle holds that transistor counts roughly double every two years, making computing cheaper and more powerful. Freeman posited that as transistors became abundant, flexibility would matter more than perfect efficiency.

He envisioned a device composed of programmable logic blocks connected through configurable routing—a chip filled with what he described as “open gates,” ready to be defined by users after manufacturing. Instead of fixing hardware in silicon permanently, engineers could configure and reconfigure circuits as requirements evolved.

Freeman sometimes compared the concept to a blank cassette tape: Manufacturers would supply the medium, while engineers determined its function. The analogy captured a profound shift in who controls the technology, shifting hardware design flexibility from chip fabrication facilities to the system designers themselves.

In 1985 Xilinx introduced the first FPGA for commercial sale: the XC2064. The device contained 64 configurable logic blocks—small digital circuits capable of performing logical operations—arranged in an 8-by-8 grid. Programmable routing channels allowed engineers to define how signals moved between blocks, effectively wiring a custom circuit with software.

Fabricated using a 2-micrometer process (meaning that 2 µm was the minimum size of the features that could be patterned onto silicon using photolithography), the XC2064 implemented a few thousand logic gates. Modern FPGAs can contain hundreds of millions of gates, enabling vastly more complex designs. Yet the XC2064 established a design workflow still used today: Engineers describe the hardware behavior digitally and then “compile the design,” a process that automatically translates the plans into the instructions the FPGA needs to set its logic blocks and wiring, according to AMD. Engineers then load that configuration onto the chip.

The breakthrough: hardware defined by memory

Earlier programmable logic devices, such as erasable programmable read-only memory, or EPROM, allowed limited customization but relied on largely fixed wiring structures that did not scale well as circuits grew more complex, Cong says.

FPGAs introduced programmable interconnects—networks of electronic switches controlled by memory cells distributed across the chip. When powered on, the device loads a bitstream configuration file that determines how its internal circuits behave.

“As process technology improved and transistor counts increased, the cost of programmability became much less significant,” Cong says.

From “glue logic” to essential infrastructure

“Initially, FPGAs were used as what engineers called glue logic,” Cong says.

Glue logic refers to simple circuits that connect processors, memory, and peripheral devices so the system works reliably, according to PC Magazine. In other words, it “glues” different components together, especially when interfaces change frequently.

Early adopters recognized the advantage of hardware that could adapt as standards evolved. In “The History, Status, and Future of FPGAs,” published in Communications of the ACM, engineers at Xilinx and organizations such as Bell Labs, Fairchild Semiconductor, IBM, and Sun Microsystems said the earliest uses of FPGAs were for prototyping ASICs. They also used it for validating complex systems by running their software before fabrication, allowing the companies to deploy specialized products manufactured in modest volumes.

Those uses revealed a broader shift: Hardware no longer needed to remain fixed once deployed.

A group dressed in business casual attire smiling and posing together around an outdoor bench adorned with a plaque. Attendees at the Milestone plaque dedication ceremony included (seated L to R) 2025 IEEE President Kathleen Kramer, 2024 IEEE President Tom Coughlin, and Santa Clara Valley Section Milestones Chair Brian Berg.Douglas Peck/AMD

Semiconductor economics changed the equation

The rise of FPGAs closely followed changes in semiconductor economics, Cong says.

Developing a custom chip requires a large upfront investment before production begins. As fabrication costs increased, products had to ship in large quantities to make ASIC development economically viable, according to a post published by AnySilicon.

FPGAs allowed designers to move forward without that larger monetary commitment.

ASIC development typically requires 18 to 24 months from conception to silicon, while FPGA implementations often can be completed within three to six months using modern design tools, Cong says. The shorter cycle and the ability to reconfigure the hardware enabled startups, universities, and equipment manufacturers to experiment with advanced architectures that were previously accessible mainly to large chip companies.

Lookup tables and the rise of reconfigurable computing

A popular technique for implementing mathematical functions in hardware isthe lookup table (LUT). A LUT is a small memory element that stores the results of logical operations, according to “LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs,” a paper selected for presentation next month at the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Instead of repeatedly recalculating outcomes, the chip retrieves answers directly from memory. Cong compares the approach to consulting multiplication tables rather than recomputing the arithmetic each time.

Research led by Cong and others helped develop efficient methods for mapping digital circuits onto LUT-based architectures, shaping routing and layout strategies used in modern devices.

As transistor budgets expanded, FPGA vendors integrated memory blocks, digital signal-processing units, high-speed communication interfaces, cryptographic engines, and embedded processors, transforming the devices into versatile computing platforms.

Why the gate arrays are distinct from CPUs, GPUs, and ASICs

FPGAs coexist with other processors because each one optimizes different priorities. Central processing units excel at general computing. Graphics processing units, designed to perform many calculations simultaneously, dominate large parallel workloads such as AI training. ASICs provide maximum efficiency when designs remain stable and production volumes are high.

“ASICs can deliver the best performance, but the development cycle is long, and the nonrecurring engineering cost can be very high. FPGAs provide a sweet spot between processors and custom silicon.” —Jason Cong, IEEE Fellow and professor of computer science at UCLA.

“FPGAs are not replacements for CPUs or GPUs,” Cong says. “They complement those processors in heterogeneous computing systems.”

Modern computing platforms increasingly combine multiple types of processors to balance flexibility, performance, and energy efficiency.

A Milestone for an idea, not just a device

This IEEE Milestone recognizes more than a successful semiconductor product. It also acknowledges a shift in how engineers innovate.

Reconfigurable hardware allows designers to test ideas quickly, refine architectures, and deploy systems while standards and markets evolve.

“Without FPGAs,” Cong says, “the pace of hardware innovation would likely be much slower.”

Four decades after the first FPGA appeared, the technology’s enduring legacy reflects Freeman’s insight: Hardware did not need to remain fixed. By accepting a small amount of unused silicon in exchange for adaptability, engineers transformed chips from static products into platforms for continuous experimentation—turning silicon itself into a medium engineers could rewrite.

Among those who attended the Milestone ceremony were 2025 IEEE President Kathleen Kramer; 2024 IEEE President Tom Coughlin; Avery Lu, chair of the IEEE Santa Clara Valley Section; and Brian Berg, history and milestones chair of IEEE Region 6 . They joined AMD’s chief executive, Lisa Su, and Salil Raje, senior vice president and general manager of adaptive and embedded computing at AMD.

The IEEE Milestone plaque honoring the field-programmable gate array reads:

“The FPGA is an integrated circuit with user-programmable Boolean logic functions and interconnects. FPGA inventor Ross Freeman cofounded Xilinx to productize his 1984 invention, and in 1985 the XC2064 was introduced with 64 programmable 4-input logic functions. Xilinx’s FPGAs helped accelerate a dramatic industry shift wherein ‘fabless’ companies could use software tools to design hardware while engaging ‘foundry’ companies to handle the capital-intensive task of manufacturing the software-defined hardware.”

Administered by the IEEE History Center and supported by donors, the IEEE Milestone program recognizes outstanding technical developments worldwide that are at least 25 years old.

Check out Spectrum’s History of Technology channel to read more stories about key engineering achievements.

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Tech

Plaud’s new earphones come with an eSIM-enabled case for talking to AI agents

Published

58 minutes ago

August 27, 2026

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Hardware companies have realized that note-taking is one of the easiest AI use cases to build for, and consequently have been busy shoving mics into everything from pendants and rings to credit-card-sized pucks and wristbands. Still, despite the variety of devices, only a few companies have been able to stand out.

One of these companies is Plaud, which has over 2.5 million people using its hardware or software. It is now launching a note-taker in a new form factor: earphones. Called Plaud One, these adopt the simple bare-bones style of Apple’s Airpods, and can record calls, while their case can be used to record in-person conversations or take notes.

Plaud isn’t the first to this form factor. Its rivals Viaim and Anker already have similar note-taking earbuds in the market.

But the company is betting on its software and AI chops to set these apart. Plaud said that once the earbuds transcribe your conversation, its AI agent — which can connect to tools like Gmail, Google Calendar, Notion and Slack — can do things like writing follow-up emails and creating documents or presentations based on the contents of the conversation.

By itself, that isn’t a unique pitch. Software note-takers like Granola, Fathom and Read AI have been offering similar workflow automation for a while now, transcribing calls and conversations, and allowing you to subsequently get an AI agent to do various tasks.

The Plaud One takes that a step further, though, with its case, which supports an eSIM card. That feature, the company says, allows users to instruct Plaud’s AI agents remotely without using their phone or computer.

The Plaud One has 12mm drivers and features active noise cancellation. The company says the case can capture voices clearly within a range of five meters, and the earphones can record six hours of in-person meetings and three hours of calls on a single charge. Combined with the case, users can record up to 25 hours of conversations on a single charge.

Buyers get 300 minutes of free transcription per month, after which they will need to buy additional plans, which start from $8.33 per month (paid annually).

That said, this launch seems to be more of a trial run. The Plaud One will be limited in quantity, as the startup likely wants to gauge demand for such AI-focused earphones before it commits to the format.

Plaud is also working on building agentic capabilities, which is expected to arrive as part of an update in the coming months. The company says it will introduce a credit-based system for different tasks, and buyers of the Plaud One will get $200 in credits for these tasks.

The company has had a good run so far, claiming in June that it had reached annual run-rate revenue of $100 million. However, competition in the market is intense, with new hardware note-takers releasing every week. Its rival, YC-backed Pocket, has also reached that milestone, and tons of other companies like Anker, Comu, Viaim, and software startup Genspark are building in the space.

Plaud’s CEO Nathan Xu holds that there should be an interface to talk to AI to invoke it from anywhere, and earbuds meet that need.

“[For AI] we need to have a wearable and an always-ready interface, one that people love to wear, is socially acceptable and private by design,” he said in a briefing.

Still, the company may find it challenging to draw people away from using their AirPods, Google Pixel Buds, Samsung Galaxy Buds, or wireless earbuds from any number of audio companies, which can pretty much do the same job when paired with any note-taking app.

But Xu says Plaud is not necessarily competing against these companies, but positioning its meeting-recording tech to adopt a popular wearable format.

Users can pre-order the device now for $249, and it will ship in the fourth quarter of 2026.

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Tech

OpenAI to start showing ads on ChatGPT’s free and Go tiers in India

Published

2 hours ago

August 27, 2026

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It seems there is no escaping the ad industry.

OpenAI said on Thursday that it will start showing ads on its ChatGPT Free and Go subscription tiers in India. The move comes after the company changed its terms of service earlier this month to indicate that it will show ads to users while they use the AI assistant.

OpenAI said in February that it has more than 100 million weekly active ChatGPT users in India, a huge chunk of whom are on the free or the lower-priced Go tiers.

The company said on Wednesday it will start by showing ads for 50 brands, and that it has partnered with agencies WPP and Omnicom for this. OpenAI will also launch an ad manager next month that will let marketers create campaigns for their companies, provided their campaigns have a daily minimum budget of ₹725 ($7.60).

“With ChatGPT Ads, businesses of every size can introduce themselves at relevant, high-context moments when decisions are beginning to take shape,” Dave Dugan, head of global ads solutions at OpenAI, said in a statement.

OpenAI has worked hard to cultivate its user base in India, launching a sub-$5 plan for ChatGPT Go in August 2025, and even running a limited promo that made that tier free for a full year. It also heavily advertised its products during sports tournaments, like the Women’s Premier League (WPL) and the Indian Premier League (IPL) cricket leagues. More recently, it hired Uber’s India head to lead its expansion efforts in the country.

The AI lab started showing ads to U.S. users in February, and expanded the program to serve ads in Europe earlier this month.

Ahead of a potential IPO, expected this year or next, OpenAI has been trying to ramp up and cement its revenue sources. According to The Wall Street Journal, the AI lab recorded revenue of $6.7 billion in the second quarter ended June 2026, up from $5.7 billion the previous quarter.

Last November, The Information reported that OpenAI was aiming to reach 220 million paying subscribers by 2030. The report said that at that time, 35 million users paid for its Plus and Pro plans.

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Tech

Nvidia closes in on Hugging Face acquisition

Published

7 hours ago

August 27, 2026

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Nvidia has agreed to buy Hugging Face for $12.9 billion, The Information reported Wednesday night, citing a source familiar with the matter. Business Insider, which first reported over the weekend that Hugging Face was fielding takeover interest, reported Wednesday night that the talks — which would value the company at more than $13 billion — had not yet produced a signed agreement and could still atomize.

TechCrunch reached out earlier to both Nvidia and Hugging Face for comment, and neither has yet responded. (Nvidia’s silence is particularly noteworthy here as the company has moved quickly in the past to address reports it considers inaccurate.)

Maybe it was destined from the start. Hugging Face, founded in 2016, is one of the most popular hubs where developers share and download open-source AI models. Buying it would give Nvidia a strong foothold in the world of open-source AI, right as open-source developers are doing their level best to catch up to closed AI systems from companies like Anthropic and OpenAI.

Why would Nvidia want that? Most obviously, it comes down to protecting its dominance in AI chips, which, from the outside at least, appears increasingly at risk, even with Nvidia’s aggressive chip-release schedule. Pretty much all of the biggest closed-source AI labs (OpenAI, Google, Amazon, and Anthropic) are now in the process of building their own AI chips to lessen their reliance on Nvidia. A thriving ecosystem of open-source AI models gives customers more alternatives to those closed labs, which in turn keeps more of the market dependent on Nvidia’s hardware. That’s also why Nvidia has already poured tens of billions of dollars into building its own open-source AI models.

Should we be surprised that Hugging Face’s days as an independent outfit appear numbered? Not really. Hugging Face CEO Clem Delangue has spent much of this year publicly aligned with Nvidia’s open-source push, amid a debate that has been building for months, as Washington officials reportedly weighed restrictions on open-weight models. (After Chinese labs like Moonshot AI released systems like its Kimi K3 model that matched leading U.S. models on benchmarks while costing a lot less to run, talk of competitive and national-security concerns appeared to grow in Washington, with some critics of closed labs — like White House advisor David Sacks — suggesting the fears were being fanned by the “duopoly” of Anthropic and OpenAI.)

In an appearance on CBS’s “Face the Nation” earlier this month, for example, Delangue said Hugging Face used an Nvidia-modified version of a Chinese open-source model to defend itself after a cyberattack and pointed to a recent letter — signed by Nvidia CEO Jensen Huang and 24 other companies, including Hugging Face — urging the U.S. government to support open models rather than restrict them. In a separate CNBC interview in late July, Delangue made similar points, citing that same letter while warning that China is “clearly dominating” open-source AI.

The deal would also mark something of a comeback for Nvidia in cloud computing. Nvidia reportedly scaled back its own cloud business, called DGX Cloud, about a year ago. But according to The Information, owning Hugging Face — which already helps developers run their AI models using rented computing power — could give Nvidia a way back into that market without starting from scratch.

There’s also a financial safety net at play. Nvidia has promised to help cover the cost of tens of billions of dollars in cloud computing deals for its customers. If those customers end up not using all the computing power they signed up for, Nvidia could get stuck with it. Owning Hugging Face would give Nvidia the ability to sell that unused capacity to Hugging Face’s customers.

The price marks a huge jump from Hugging Face’s last known value. The company raised $235 million in 2023 in a funding round that valued it at $4.5 billion. That round was led by Salesforce Ventures, with money also coming from Alphabet’s GV, IBM Ventures, and Nvidia itself, among others.

This wouldn’t be Hugging Face’s first brush with an Nvidia offer, either. Hugging Face turned down a $500 million investment offer from Nvidia late last year that would have valued it at $7 billion, the Financial Times previously reported. Hugging Face said at the time it didn’t want a dominant investor that could sway its decisions.

As for why it would say yes now, one could argue that a buyout is different from taking on one giant backer — a scenario that often means ceding control while being pressured to continue growing.

Hugging Face is also still a comparatively small business by revenue in the world of AI. The Information reported it was recently generating about $150 million a year in revenue, up from roughly $100 million just two months earlier.

That growth has enabled the company to get “close to profitability,” as Delangue told TechCrunch last month. Still, a price near $13 billion would be a massive multiple for a company this size and hard to resist.

Not last, the deal would give Hugging Face access to Nvidia’s much deeper pockets just as other, AI infrastructure competitors start to get pulled into other outfits, as suggested by Stripe’s recent deal to acquire OpenRouter, a startup founded in early 2023 that helps customers select different AI models to perform different tasks depending on their needs and budget.

OpenRouter was valued at just $1.3 billion back in May during its Series B round. Stripe reportedly paid more than $7 billion to make it its own earlier this month.

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